Description
The EDS2508AP is a 256M bits SDRAM organized as 8,388,608 words × 8 bits × 4 banks.
DQ0 VDD
2
3
4
5
6
B
DQ14 VSSQ (NC)
VDDQ DQ1 (NC)
DQ2 (DQ1)
Features
- r>.
- 3.3V power supply Clock frequency: 133MHz (max. ) LVTTL interface Single pulsed /RAS 4 banks can operate simultaneously and independently.
- Burst read/write operation and burst read/single write operation capability.
- Programmable burst length (BL): 1, 2, 4, 8, full page.
- 2 variations of burst sequence Sequential (BL = 1, 2, 4, 8) Interleave (BL = 1, 2, 4, 8).
- Programmable /CAS latency (CL): 2, 3.
- Byte cont.
EDS2508APSA Datasheet
