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HB54R1G9F2U - 1GB Registered DDR SDRAM DIMM

Datasheet Summary

Description

The HB54R1G9F2U is a 128M × 72 × 2 bank Double Data Rate (DDR) SDRAM Module, mounted 36 pieces of 256Mbits DDR SDRAM (HM5425401BTB) sealed in TCP package, 1 piece of PLL clock driver, 2 pieces of register driver and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD).

Features

  • 184-pin socket type package (dual lead out)  Outline: 133.35mm (Length) × 30.48mm (Height) × 4.80mm (Thickness)  Lead pitch: 1.27mm.
  • 2.5V power supply (VCC/VCCQ).
  • SSTL-2 interface for all inputs and outputs.
  • Clock frequency: 143MHz/133MHz/125MHz (max. ).
  • Data inputs and outputs are synchronized with DQS.
  • 4 banks can operate simultaneously and independently (Component).
  • Burst read/write operation.
  • Programmable burst length:.

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Datasheet Details

Part number HB54R1G9F2U
Manufacturer Elpida Memory
File Size 159.80 KB
Description 1GB Registered DDR SDRAM DIMM
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DATA SHEET 1GB Registered DDR SDRAM DIMM HB54R1G9F2U-A75B/B75B/10B (128M words × 72 bits, 2 Banks) Description The HB54R1G9F2U is a 128M × 72 × 2 bank Double Data Rate (DDR) SDRAM Module, mounted 36 pieces of 256Mbits DDR SDRAM (HM5425401BTB) sealed in TCP package, 1 piece of PLL clock driver, 2 pieces of register driver and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD). Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2-bit prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable.
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