DD2508AETA Datasheet - Elpida

DD2508AETA EDD2508AETA

DATA SHEET 256M bits DDR SDRAM EDD2508AETA (32M words × 8 bits) EDD2516AETA (16M words × 16 bits) Specifications Density: 256M bits Organization  8M words × 8 bits × 4 banks (EDD2508AETA) www.DataSheet4U.com  4M words × 16 bits × 4 banks (EDD2516AETA) Package: 66-pin plastic TSOP (II)  Lead-free (RoHS compliant) Power supply:  DDR400: VDD, VDDQ = 2.6V ± 0.1V  DDR333, 266: VDD, VDDQ = 2.5V ± 0.2V Data rate: 400Mbps/333Mbps/266Mbps (max.)

DD2508AETA Features

* Double-data-rate architecture; two data transfers per clock cycle

* The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture

* Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver

* Data

DD2508AETA_Elpida.pdf