* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture
* Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver
* Data
DD2508AETA Datasheet (648.64 KB)
DD2508AETA
Elpida
648.64 KB
edd2508aeta.
DATA SHEET
256M bits DDR SDRAM
EDD2508AETA (32M words × 8 bits) EDD2516AETA (16M words × 16 bits)
Specifications
* Density: 256M bits
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