EDW2032BBBG - 2G bits GDDR5 SGRAM

Product Overview

Elpida

Datasheet Details

Part number	EDW2032BBBG
Manufacturer	Elpida
File Size	245.77 KB
Description	2G bits GDDR5 SGRAM
Datasheet	EDW2032BBBG Datasheet
Additional preview pages of the EDW2032BBBG datasheet.

Product details

Description

Table 1: Signal Description Signal CK, /CK Type Input WCK01, /WCK01, WCK23, /WCK23 Input /CKE Input /CS Input /RAS, /CAS, /WE Input BA0 - BA3 Input A0 - A12 Input DQ0 - DQ31 /DBI0 - /DBI3 I/O I/O EDC0 - EDC3 /ABI ZQ /RESET MF SEN VREFC VREFD VDDQ VSSQ VDD VSS NC Output Input - Input Input Input Supply Supply Supply Supply Supply Supply - Detailed Function Clock: CK and /CK are differential clock inputs.Command inputs are latched on the rising edge of CK.Address inputs are lat

Features

Density: 2G bits.
Organization.
4Mbit x 32 I/O x 16 banks.
8Mbit x 16 I/O x 16 banks.
Package.
170-ball FBGA.
Lead-free (RoHS compliant) and Halogen-free.
Power supply:.
VDD: 1.6V/1.5V ± 3% and 1.35V ± 3%.
VDDQ: 1.6V/1.5V ± 3% and 1.35V ± 3%.
Data rate: 7.0Gbps/6.0Gbps/5.0Gbps (max. ).
16 internal banks.
Four bank groups for tCCDL = 3tCK.
8n prefetch architecture: 256 bi.

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Published: Aug 13, 2015 |