* Description
* Internal Double-Date-Rate architecture with twice accesses per clock cycle.
* Single 2.5V ±0.2V Power Supply
* 2.5V SSTL-2 compatible I/O
* Burst Length (B/L) of 2, 4, 8
* 2.5, 3 clock read latency
* Bi-directional, intermittent data st
EM42AM1684RTC Datasheet (335.91 KB)
EM42AM1684RTC
Eorex
335.91 KB
Double data rate sdram.
Revision History
Revision 0.1 (Jul. 2010) - First release.
Revision 0.2 (Sep. 2010) - Delete CL=2, page 2, 8, 17 - Add 166MHz@2.5-3-3; 200MHz@3-3-3, p.
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