7420
Fairchild Semiconductor
159.85kb
Dual 4-input nand gates.
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7420 - Dual 4-Input Positive NAND Gate
(NTE)
NTE7420 Integrated Circuit TTL − Dual 4−Input Positive NAND Gate
Description: The NTE7420 contains two independent 4−Input NAND gates in a 14−Lead pl.
7421 - Dual 4-Input Positive AND Gate
(Fairchild Semiconductor)
.
74221 - Dual non-retriggerable monostable multivibrator
(NXP)
INTEGRATED CIRCUITS
DATA SHEET
For a plete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 .
74221 - Dual Non-Retriggerable Monostable Multivibrator
(Fairchild Semiconductor)
MM74HC221A Dual Non-Retriggerable Monostable Multivibrator
September 1983 Revised February 1999
MM74HC221A Dual Non-Retriggerable Monostable Multivi.
74221 - Dual Monostable Multivibrators
(Hitachi Semiconductor)
HD74HC221
Dual Monostable Multivibrators (with Schmitt Trigger Input)
Description
Each multivibrator features both a negative, A, and a positive, B, .
7423 - Dual 4-Input NOR Gate
(Texas Instruments)
.ti.
PACKAGE OPTION ADDENDUM
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
5962-9763601QEA JM38510/00403BCA JM38510/00403BCA
SN5423J SN54.
74240 - Octal 3-STATE Buffer/Line Driver/Line Receiver
(Fairchild Semiconductor)
DM74LS240 • DM74LS241 Octal 3-STATE Buffer/Line Driver/Line Receiver
August 1986 Revised March 2000
DM74LS240 • DM74LS241 Octal 3-STATE Buffer/Line .
74240 - Eight three-state inverting buffer / line driver / line receiver
(San Mao)
54/74240
//(3S,) : 240 , 54/74S240 54/74LS240 ,( ): 54S240/74S240 54LS240/74LS240 : 1A，2A /1G,/2G 1Y~8Y : tPLH 4.5ns 9ns tphl 4.5ns 12ns PD 450mW 10.
74244 - Octal 3-STATE Buffer/Line Driver/Line Receiver
(Fairchild Semiconductor)
DM74LS244 Octal 3-STATE Buffer/Line Driver/Line Receiver
August 1986 Revised March 2000
DM74LS244 Octal 3-STATE Buffer/Line Driver/Line Receiver
Gen.
74244 - Octal 3-STATE Buffer/Line Driver/Line Receiver
(ETC)
V cc 20
G(2) B1(1) A1(2) B2(1) A2(2) B3(1) A3(2) B4(1) A4(2) 18 17 16 15 14 13 12 11 19
1 2 3 4 5 6 7 8 9 10 G(1) A1(1) B1(2) A2(1) B2(2) A3(1) B3(2.
