* s 5V tolerant inputs s 2.3V
* 3.6V VCC specifications provided s 7.5 ns tPD max (VCC = 3.3V), 10 µA ICC max s Power down high impedance inputs and outputs s ±24 mA output drive (VCC = 3.0V) s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performa
74LCX112 Datasheet (124.96 KB)
74LCX112
Fairchild Semiconductor
124.96 KB
Low voltage dual j-k negative edge-triggered flip-flop.
74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs June 1998 Revised February 2001 74LCX112 Low Voltage Dual J-.
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