Description
of Changes
© Freescale Semiconductor, Inc., 2005. All rights reserved.This product incorporates SuperFlash® Technology licensed from SST.DataSheet 4 U .com
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List of Chapters
Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Appendix A Appendix B Device Overview  19 External Signal Description  23 Modes of Operation  31 Memory Map and Register De
Features
- 8-Bit HCS08 Central Processor Unit (CPU).
 
- 20-MHz HCS08 CPU (central processor unit) HC08 instruction set with added BGND instruction Background debugging system Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) Debug module containing two comparators and nine trigger modes. Eight deep FIFO for storing change-of-flow addresses and event-only data Debug module supports both.