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MC9S12K - Microcontrollers

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MC9S12K Product details

Description

of Changes Change load cap value on VDD and VDDPLL.Correct expanded bus timing from 20MHz to 25 MHz.Move ATD interrupt vector from $ffd0 to $ffd2. Change PWeh and tDSW parameter in external bus timing.Expand to a K-Family SoC Guide and include 9S12KT256. Replace 16-channel ATD with two 8-channel ATDs for 9S12KT256. Changed to a Device User Guide and added Document number.Updated Table A-17 Oscillator Characteristics.Replaced XCLKS with PE7 for Clock Selection diagrams.Added CTRL to Table 2

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