MB90V520, MB90F523 Datasheet - Fujitsu Media Devices

Features

* Clock Embedded PLL clock multiplication circuit Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz). The system can be operated by a sub-clock (rated at 32.768 kHz). Minimum instruction