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GS815018AB-357 - 1M x 18/ 512K x 36 18Mb Register-Register Late Write SRAM

Datasheet Summary

Description

250 MHz

Because GS815018/36A are synchronous devices, address data inputs and read/write control inputs are captured on the rising edge of the input clock.

Write cycles are internally self-timed and initiated by the rising edge of the clock input.

Features

  • Register-Register Late Write mode, Pipelined Read mode.
  • 2.5 V +200/.
  • 200 mV core power supply.
  • 1.5 V or 1.8 V HSTL Interface.
  • ZQ controlled programmable output drivers.
  • Dual Cycle Deselect.
  • Fully coherent read and write pipelines.
  • Byte write operation (9-bit bytes).
  • Differential HSTL clock inputs, K and K.
  • Asynchronous output enable.
  • Sleep mode via ZZ.
  • IEEE 1149.1 JTAG-compliant Serial Boun.

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Datasheet preview – GS815018AB-357

Datasheet Details

Part number GS815018AB-357
Manufacturer GSI Technology
File Size 1.29 MB
Description 1M x 18/ 512K x 36 18Mb Register-Register Late Write SRAM
Datasheet download datasheet GS815018AB-357 Datasheet
Additional preview pages of the GS815018AB-357 datasheet.

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Full PDF Text Transcription

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Product Preview GS815018/36AB-357/333/300/250 www.DataSheet4U.com 119-Bump BGA Commercial Temp Industrial Temp Features • Register-Register Late Write mode, Pipelined Read mode • 2.5 V +200/–200 mV core power supply • 1.5 V or 1.8 V HSTL Interface • ZQ controlled programmable output drivers • Dual Cycle Deselect • Fully coherent read and write pipelines • Byte write operation (9-bit bytes) • Differential HSTL clock inputs, K and K • Asynchronous output enable • Sleep mode via ZZ • IEEE 1149.1 JTAG-compliant Serial Boundary Scan • JEDEC-standard 119-bump BGA package • Pb-Free 119-bump BGA package available 1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM Functional Description 250 MHz–357 MHz 2.
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