A3-44PA-2SV Datasheet - Hirose Electric

A3-44PA-2SV HEADER CONNECTOR

Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 DQS0 ~ DQS17 CK0,CK0 ~ CK2, CK2 CKE0, CKE1(for double banks) CS0, CS1(for double banks) RAS CAS WE CB0 ~ CB7 Function Address input (Multiplexed) Bank Select Address Data input/output Data Strobe input/output Clock input Clock enable input Chip select input Row.

www.DataSheet4U.com 512MB, 1GB, 2GB Registered DIMM Preliminary DDR SDRAM DDR SDRAM Registered Module 184pin Registered Module based on 512Mb C-die with 72-bit ECC 66 TSOP-II and 60 ball FBGA with Pb-Free (RoHS compliant) DataSheet4U.com DataShee Revision 0.1 October. 2004 Rev. 0.1 October, 2004 DataSheet4U.com www.DataSheet4U.com 512MB, 1GB, 2GB Registered DIMM Revision History Revision 0.0 (September, 2004) - First release Revision 0.1 (October, 2004) - Changed IDD current. Prelimi.

A3-44PA-2SV Features

* 28M x 72 ECC Module (M312L2920CUS) (Populated as 1 bank of x4 DDR SDRAM Module) Functional Block Diagram VSS RCS0 DQS0 DQ0 DQ1 DQ2 DQ3 DQS1 DQ8 DQ9 DQ10 DQ11 DQS2 DQ16 DQ

A3-44PA-2SV Datasheet (712.74 KB)