Description
Description of time specification amended Figure amended Figure amended Amended Initial values amended
1. IRQ edge select register (IEGR) Bits 4 to 2 amended 62 63 to 65 65 67, 68 3.3.5 Interrupt Operations 3.4.2 Notes on Rewriting Port Mode Registers 3.4.3 Interrupt Request Flag Clearing Methods 74 79 2. Interrupt enable register 1 (IENR1) 3. Interrupt enable register 2 (IENR2) 4. Interrupt request register 1 (IRR1) 5. Interrupt request register 2 (IRR2) Figure 3.3 Flow up to Interrupt Accepta
Features
- Figure 2.16(2) H8/3801 Memory Map Figure 2.16(3) H8/3800 Memory Map Table 3.2 Interrupt Sources and Their Priorities Table 3.3 Interrupt Control Registers.