HD6417718R Datasheet - Hitachi

HD6417718R - MICROPROCESSOR

added Added description of wait state timing when WAITSEL is set to 1 Figure 11.30 Synchronous DRAM Auto-Refresh RD/WR waveform amended Timing 11.4.1 When Area 6 is Designated for PCMCIA, New sections added with a 16-Bit Bus Width 11.4.2 Self-Refreshing 11.4.3 PCMCIA Area Access Table 13.1 RTC Pin .

w w w .D at SuperH™ RISC engine SH7718R Hardware Manual h S a t e e 4U . m o c ADE-602-103A Rev. 2.0 3/11/00 Hitachi, Ltd. w w w a .D S ta e h U 4 t e .c m o w w w .D a S a t e e h U 4 t m o .c Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise w.

HD6417718R Features

* Revisions (See Manual for Details) Hardware standby mode added to power-down modes Product lineup addition

* Pin arrangement positions amended (entire figure rotated 90° so that pin 1 is at bottom left)

* Correction of pins 107, 126, and 129 56 192 2.6 Usage Note 10.11 Notes on Board

HD6417718R_Hitachi.pdf