HY57V641620ET
description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.5 / Feb. 2005 1 m o .c U 4 t e e h S a at .D w w w
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P)-x I Series
DESCRIPTION
The Hynix HY57V641620E(L/S)T(P) series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY57V641620E(L/S)T(P) is organized as 4banks of 1,048,576x16. HY57V641620E(L/S)T(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are patible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a...
