HY57V641620ET - 4-Bank x 1M x 16-Bits SDRAM
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Rev.
1.5 / Feb.
2005 1 m o .c U 4 t e e h S a at .D w w w Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P)-xI Series DESCRIPTION The Hyni
m o c .
64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O U 4 t e e Document Title h S a Revision at History .D w w w 4Bank x 1M x 16bits Synchronous DRAM Revision No.
History First Version Release 1.0 1.
Changed tOH: 2.0 > 2.5 [tCK = 7 & 7.5 (CL3) Product] 1.1 1.
Changed Input High/Low Voltage (Page 08) 2.
Changed DC characteristics (Page 09) - IDD2NS: 18mA -> 15mA - IDD5:210 / 195 / 180mA -> 170 / 160 / 150mA [Speed 200 / 166 / 143 / 133MHz] 3.
Changed Clock High / Low pulse width Tim
HY57V641620ET Features
* Voltage: VDD, VDDQ 3.3V supply voltage All device pins are compatible with LVTTL interface 54 Pin TSOPII (Lead or Lead Free Package) All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM, LDQM
