* JEDEC standard Double Data Rate2 Synchrnous DRAMs (DDR2 SDRAMs) with 1.8V +/ - 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface 8 Bank architecture Posted CAS Programmable CAS Latency 3 ,4 ,5, 6 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Terminati
HYMP112U64CR8-Y5 Datasheet (252.14 KB)
HYMP112U64CR8-Y5
Hynix Semiconductor
252.14 KB
240pin ddr2 sdram unbuffered dimms based on 1gb c version.
240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb C version This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 1Gb version C DDR2.
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