8P79818 Datasheet (IDT) - Programmable Low Additive Jitter 2:8 Buffer

8P79818, Programmable Low Additive Jitter 2:8 Buffer

The device is intended to take 1 or 2 reference clocks, select between them, using a pin or register selection and generate up to 8 outputs that may be the same as the reference frequency or integer-divider versions of it.

The 8P79818 supports two output banks, each with its own divider and power su

8P79818 Features

* ▪ Two differential inputs support LVPECL, LVDS, HCSL or LVCMOS reference clocks

* Accepts input frequencies ranging from 1PPS (1Hz) to 700MHz ▪ Select which of the two input clocks is to be used as the reference clock for which divider via pin or register selection

* Switchover will