IW4042B - Quad Clocked D-Latch
TECHNICAL DATA IW4042B Quad Clocked «D» Latch High-Voltage Silicon-Gate CMOS IW4042B types contain four latch circuits, each strobed by a common clock.
Complementary buffered outputs are available from each circuit.
The impedance of the n- and p-channel output devices is balanced and all outputs are electrically identical.
Information present at the data input is transferred to outputs Q and Q during the CLOCK level which is programmed by the POLARITY input.
For POLARITY = 0 the transfer occur
