ESD5V5U5ULC Datasheet - Infineon

ESD5V5U5ULC TVS Diodes

Pin 6 Pin 5 Pin 4 SC74 Pin 1 Pin 3 Pin 4 Pin 5 Pin 6 Pin 1 Pin 2 Pin 3 a) Pin configuration Figure 1 Pin Configuration and Schematic Diagram GND Pin 2 b) Schematic diagram ESD5V5U5ULC_PinConf_and_SchematicDiag.vsd Table 1 Ordering Information Type Package ESD5V5U5ULC SC74 Configuration.

TVS Diodes Transient Voltage Suppressor Diodes ESD5V5U5ULC Ultra-low Capacitance ESD / Transient / Surge Protection Array ESD5V5U5ULC Data Sheet Revision 1.3, 2015-07-16 Final Power Management & Multimarket Edition 2015-07-16 Published by Infineon Technologies AG 81726 Munich, Germany © 2015 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examp.

ESD5V5U5ULC Features

* ESD / Transient protection of high speed data lines exceeding

* IEC61000-4-2 (ESD): ±25 kV (air / contact)

* IEC61000-4-4 (EFT): ±2.5 kV / ±50 A (5/50 ns)

* IEC61000-4-5 (surge): ±6 A (8/20 μs)

* Maximum working voltage: VRWM = 5.5 V

* Extremely low

ESD5V5U5ULC Datasheet (322.88 KB)