IT8152G, IT8152F Datasheet - Integrated Technology Express

IT8152G Risc to Pci Companion Chip

was added in I/O cell section. The PCICR default was revised to 00000168h in Table 7-1. Bit 0 description was revised in section 7.2.1 SDRAM Control Register. The default value of bit 7 was revised to 0 in section 7.2.2 PCI Slave Control Register. The default value of bit 3 was revised to 1000 in se.

w w a D . w S a t e e h U 4 t m o .c IT8152F / IT8152G Advanced RISC-to-PCI Companion Chip Preliminary Specification V0.3.4 w w w t a .D S a e h U 4 t e .c m o w w w .D a S a t e e h U 4 t m o .c Copyright © 2001 ITE, Inc. This is Preliminary document release. All specifications are subject to change without notice. The material contained in this document supersedes all previous documentation issued for the related products included herein. Please contact ITE, Inc. fo.

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