N82C55A Datasheet - Intel Corporation

N82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE

Symbol PA3 *0 RD CS Pin Number Dip PLCC 1 * 4 5 6 2 *5 6 7 Type I O I I Name and Function PORT A PINS 0 * 3 Lower nibble of an 8-bit data output latch buffer and an 8-bit data input latch READ CONTROL This input is low during CPU read operations CHIP SELECT A low on this.

82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE Y Compatible with all Intel and Most Other Microprocessors High Speed ‘‘Zero Wait State’’ Operation with 8 MHz 8086 88 and 80186 188 24 Programmable I O Pins Low Power CHMOS Completely TTL Compatible Y Y Y Control Word Read-Back Capability Direct Bit Set Reset Capability 2 5 mA DC Drive Capability on all I O Port Outputs Available in 40-Pin DIP and 44-Pin PLCC Available in EXPRESS Standard Temperature Range Extended Temperature Range Y Y Y Y Y .

N82C55A Features

* or ‘‘personality’’ to further enhance the power and flexibility of the 82C55A Port A One 8-bit data output latch buffer and one 8-bit input latch buffer Both ‘‘pull-up’’ and ‘‘pulldown’’ bus hold devices are present on Port A Port B One 8-bit data input output latch buffer Only ‘‘pull-up’’ bus hold

N82C55A_IntelCorporation.pdf