UPI-C42 Datasheet - Intel Corporation

UPI-C42 UNIVERSAL PERIPHERAL INTERFACE CHMOS 8-BIT SLAVE MICROCONTROLLER

Symbol TEST 0 TEST 1 DIP Pin No 1 39 PLCC Pin No 2 43 QFP Pin No 18 16 Type I Name and Function TEST INPUTS Input pins which can be directly tested using conditional branch instructions FREQUENCY REFERENCE TEST 1 (T1) functions as the event timer input (under software control) TEST 0 (T0) is a multi.

UPI-C42 UPI-L42 UNIVERSAL PERIPHERAL INTERFACE CHMOS 8-BIT SLAVE MICROCONTROLLER Y Y Y Y Y Y Pin Software and Architecturally Compatible with all UPI-41 and UPI-42 Products Low Voltage Operation with the UPIL42 Full 3 3V Support Hardware A20 Gate Support Suspend Power Down Mode Security Bit Code Protection Support 8-Bit CPU plus ROM OTP EPROM RAM I O Timer Counter and Clock in a Single Package 4096 x 8 ROM OTP 256 x 8 RAM 8-Bit Timer Counter 18 Programmable I O Pins DMA Interrupt or Polled Op.

UPI-C42 Features

* of the NMOS family plus a larger user programmable memory array (4K) hardware A20 gate support and lower power consumption inherent to a CHMOS product The UPI-L42 offers the same functionality and socket compatibility as the UPI-C42 as well as providing low voltage 3 3V operation The UPI-C42 is esse

UPI-C42 Datasheet (345.87 KB)