M82380 Datasheet - Intel

M82380 HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS

3 2 Interface Signals 3 2 1 DREQn and EDACK (0 * 2) 3 2 2 HOLD and HLDA 3 2 3 EOP 3 3 Modes of Operation 3 3 1 Target Requester Definition 3 3 2 Buffer Transfer Processes 3 3 3 Data Transfer Modes 3 3 4 Channel Priority Arbitration 3 3 5 Combining Priority Modes 3 3 6 Bus Operation 3 4 Bus A.

M82380 HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS Y High Performance 32-Bit DMA Controller 40 Mbytes sec Maximum Data Transfer Rate at 20 MHz 8 Independently Programmable Channels 20-Source Interrupt Controller Individually Programmable Interrupt Vectors 15 External 5 Internal Interrupts M8259A Superset Four 16-Bit Programmable Interval Timers M82C54 Compatible Programmable Wait State Generator 0 to 15 Wait States Pipelined 1 to 16 Wait States Non-Pipeline.

M82380 Features

* of the M82380 Each module has a corresponding detailed section later in this data sheet Those sections should be referred to for design and programming information 1 1 M82380 Architecture The M82380 is comprised of several computer system functions that are normally found in separate LSI and VLSI c

M82380_IntelCorporation.pdf