CP82C84A Datasheet - Intersil Corporation

CP82C84A CMOS Clock Generator Driver

SYMBOL NUMBER TYPE DESCRIPTION AEN1, AEN2 3, 7 I ADDRESS ENABLE: AEN is an active LOW signal. AEN serves to qualify its respective Bus Ready Signal (RDY1 or RDY2). AEN1 validates RDY1 while AEN2 validates RDY2. Two AEN signal inputs are useful in system configurations which permit the processo.

Data Sheet September 9, 2015 82C84A FN2974.4 CMOS Clock Generator Driver The Intersil 82C84A is a high performance CMOS Clock Generator-driver which is designed to service the requirements of both CMOS and NMOS microprocessors such as the 80C86, 80C88, 8086 and the 8088. The chip contains a crystal controlled oscillator, a divide-by-three counter and complete “Ready” synchronization and reset logic. Static CMOS circuit design permits operation with an external frequency source from DC to 25MH.

CP82C84A Features

* Generates the System Clock For CMOS or NMOS Microprocessors

* Up to 25MHz Operation

* Uses a Parallel Mode Crystal Circuit or External Frequency Source

* Provides Ready Synchronization

* Generates System Reset Output From Schmitt Trigger Input

* TTL

CP82C84A Datasheet (274.32 KB)