LPR520 Datasheet - LOGIC Devices Incorporated

LPR520 4 x 16-bit Multilevel Pipeline Register

The LPR520 is functionally compatible with the L29C520 but have 16-bit inputs and outputs. The LPR520 is implemented in low power CMOS. The LPR520 contains four registers which can be configured as two independent, 2-level pipelines or as one 4-level pipeline. The Instruction pins, I1-0, control the.

LPR520 Features

* u Four 16-bit Registers u Implements Double 2-Stage Pipeline or Single 4-Stage Pipeline Register u Hold, Shift, and Load Instructions u Separate Data In and Data Out Pins u High-Speed, Low Power CMOS Technology u Three-State Outputs u 44-pin PLCC, J-Lead LPR520 BLOCK DIAGRAM REGISTER 1 REGISTER 2

LPR520_LOGICDevicesIncorporated.pdf