ORSPI4 Datasheet - Lattice Semiconductor

ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC

ORCA® ORSPI4 www.DataSheet4U.com Dual SPI4 Interface and High-Speed SERDES FPSC October 2007 Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconﬁgurable embedded System-on-a-Chip (SoC) architecture, the ORSPI4 FPSC contains two SPI4.2 interface blocks, a high-speed Memory Controller, four channels of 0.6-3.7 Gbits/s SERDES with 8b/10b encoding and decoding and over 600K programmable system gates all on a si.

ORSPI4 Features

* OIF-SPI4-02.0 compliant interfaces Dynamic timing receive interface:

* Full bandwidth up to 450 MHz DDR (900 Mbits/s) for all speed grades.

* Bit de-skewing up to 16 phases of the clock

* Capable of aligning bit-to-bit skews as large as ±1 bit periods Stat

ORSPI4_LatticeSemiconductor.pdf