iCE40 Datasheet (Lattice) - Ultra-low power FPGA and sensor manager

iCE40, Ultra-low power FPGA and sensor manager

iCE40 LP/HX Family Data Sheet FPGA-DS-02029-3.7 March 2021 iCE40 LP/HX Family Data Sheet Disclaimers Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose.

All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely with Buyer.

Buyer shall not rely on any data and performance specifications or parameters prov

iCE40 Features

* 7 2. Product Family 8 3. Architecture9 3.1. Architecture Overview 9 3.1.1. PLB Blocks 10 3.1.2. Routing11 3.1.3. Clock/Control Distribution Network 11 3.1.4. sysCLOCK Phase Locked Loops (PLLs) 12 3.1.5. sysMEM Embedded Block RAM Memory 13 3.1.6. sysI/O 15 3.1.7. sysI/O Buffer 18 3.1.8. Non-Volati