MIPS324KEP - Processor Core

MIPS Technologies

Datasheet Details

Part number	MIPS324KEP
Manufacturer	MIPS Technologies
File Size	410.01 KB
Description	Processor Core
Datasheet	MIPS324KEP_MIPSTechnologies.pdf

5-stage pipeline.
32-bit Address and Data Paths.
MIPS32-Compatible Instruction Set.
Multiply-Accumulate and Multiply-Subtract Instructions (MADD, MADDU, MSUB, MSUBU) Targeted Multiply Instruction (MUL) Zero/One Detect Instructions (CLZ, CLO) Wait Instruction (WAIT) Conditional Move Instructions (MOVZ, MOVN) Prefetch Instruction (PREF).
Simple Fixed Mapping Translation (FMT) mechanism.
Simp.

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Published: May 4, 2006 |