* formance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops
MMSF4205 Datasheet (191.42 KB)
MMSF4205
MMSF4205
191.42 KB
Tmos single p-channel fet.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Medium Power Surface Mount Products
TMOS Single P-Channel Field Effect Trans.
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