SY100E101
FEATURES s 500ps max. propagation delay s Extended 100E VEE range of
- 4.2V to
- 5.5V s True and plementary outputs s Fully patible with industry standard 10KH,
100K I/O levels s Internal 75KΩ input pulldown resistors s Fully patible with Motorola MC10E/100E101 s Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E101 are quad 4-input OR/NOR gates designed for use in new, high-performance ECL systems. The E101 features both true and plementary outputs.
BLOCK DIAGRAM
PIN NAMES
Pin Dna, Dnb, Dnc, Dnd Q0-Q3 Q0-Q3 VCCO
Function Data Inputs True Outputs Inverting Outputs VCC to Output
M9999-032006 hbwhelp@micrel. or (408) 955-1690
Rev.: G Amendment: /0 Issue Date: March 2006
Micrel, Inc.
SY10E101 SY100E101
PACKAGE/ORDERING INFORMATION
28-Pin PLCC (J28-1)
Ordering Information(1)
Part Number SY10E101JI SY10E101JITR(2) SY100E101JI SY100E101JITR(2)
SY10E101JC SY10E101JCTR(2) SY100E101JC SY100E101JCTR(2) SY10E101JY(3)
Package Operating
Type
Range
J28-1 Industrial
J28-1...
