SY100E112
FEATURES s 600ps max. propagation delay s Extended 100E VEE range of
- 4.2V to
- 5.5V s mon enable input s Fully patible with industry standard 10KH, 100K
I/O levels s Internal 75KΩ input pulldown resistors s Fully patible with Motorola MC10E/100E112 s Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E112 are quad drivers designed for use in new, high-performance ECL systems. The E112 has two pairs of OR/NOR outputs from each gate and a mon, buffered enable input. The data input can also be used as an ECL memory address fan-out driver, although the E111 is designed specifically for this purpose, and offers lower skew than the E112. For memory address driver applications where scan capabilities are required, please refer to the SY10/100E212 device.
BLOCK DIAGRAM
D0 D1 D2 D3 EN
PIN NAMES
Pin Q0a Q0b D0-D3 Q0a EN Q0b Qna, Qnb
Qna, Qnb Q1a VCCO Q1b Q1a Q1b
Q2a Q2b Q2a Q2b
Q3a Q3b Q3a Q3b
Function Data Inputs Enable Input True Outputs Inverting Outputs VCC to Output
M9999-032006...
