SY100E167 Datasheet (Micrel Semiconductor)

SY100E167, 6-BIT 2:1 MUX-REGISTER

The SY10/100E167 offer six 2:1 multiplexers followed by D flip-flops with single-ended outputs, designed for use in new, high-performance ECL systems.

The Select (SEL) control allows one of the two data inputs to the multiplexer to pass through.

The two external clock signals (CLK1, CLK2) are gated

SY100E167 Features

* s s s s s s s s s s s 1000MHz min. operating frequency Extended 100E VEE range of

* 4.2V to

* 5.5V 800ps max. clock to output Single-ended outputs Asynchronous Master Reset Dual clocks Fully compatible with industry standard 10KH, 100K ECL levels Internal 75KΩ input pulldown resistors