SY100E167 Datasheet | Micrel Semiconductor

FEATURES s s s s s s s s s s s 1000MHz min. operating frequency Extended 100E VEE range of - 4.2V to - 5.5V 800ps max. clock to output Single-ended outputs Asynchronous Master Reset Dual clocks Fully patible with industry standard 10KH, 100K ECL levels Internal 75KΩ input pulldown resistors ESD protection of 2000V Fully patible with Motorola MC10E/100E167 Available in 28-pin PLCC package DESCRIPTION The SY10/100E167 offer six 2:1 multiplexers followed by D flip-flops with single-ended outputs, designed for use in new, high-performance ECL systems. The Select (SEL) control allows one of the two data inputs to the multiplexer to pass through. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as control for the six flip-flops. The selected data are transferred to the flip-flops on the rising edge of CLK1 or CLK2 (or both). The multiplexer operation is controlled by the Select (SEL) signal which selects one of the two bits of input data at each...