SY10E256
FEATURES s 950ps max. data to output s Extended 100E VEE range of
- 4.2V to
- 5.5V s 850ps max. latch enable to output s Separate select controls s Differential outputs s Fully patible with industry standard 10KH,
100K ECL levels s Internal 75KΩ input pulldown resistors s Fully patible with Motorola MC10E/100E256 s Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E256 offer three 4:1 multiplexers followed by latches with differential outputs designed for use in new, high-performance ECL systems. Separate Select controls are provided for the leading 2:1 mux pairs (see block diagram).
When the Latch Enable (LEN) is at a logic LOW, the latch is transparent and output data is controlled by the multiplexer select controls. A logic HIGH on LEN latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW.
BLOCK DIAGRAM
D0a D0b D0c D0d
D1a D1b D1c D1d
D2a D2b D2c D2d
SEL1A
SEL1B
SEL2
D E NR
D E NR
D E NR
Q0 Q0
Q1 Q1
Q2 Q2
PIN NAMES
Pin D0x-...
