MT4LC1M16E5 Datasheet - Micron Technology

MT4LC1M16E5 EDO DRAM

The 1 Meg x 16 is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x16 configuration. The 1 Meg x 16 has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins (CASL# and CASH#). These function like a single CAS# found on other DRAMs in that either CASL# or C.

MT4LC1M16E5 Features

* JEDEC- and industry-standard x16 timing, functions, pinouts, and packages

* High-performance CMOS silicon-gate process

* Single power supply (+3.3V ±0.3V or 5V ±10%)

* All inputs, outputs and clocks are TTL-compatible

* Refresh modes: RAS#-ONLY, CAS#-BEFORE-

MT4LC1M16E5 Datasheet (385.15 KB)