Description
ADVANCE‡ www.DataSheet4U.com 4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM 36Mb QDR™II SRAM 2-WORD BURST .
4 Meg x 8, QDRIIb2 FBGA 4 Meg x 9, QDRIIb2 FBGA 2 Meg x 18, QDRIIb2 FBGA 1 Meg x 36, QDRIIb2 FBGA
OPTIONS.
Clock Cycle Timing 4ns (250 MHz).
Features
* DLL circuitry for accurate output data placement
MT54W4MH8B MT54W4MH9B MT54W2MH18B MT54W1MH36B
Figure 1 165-Ball FBGA
* Separate independent read and write data ports with concurrent transactions
* 100 percent bus utilization DDR READ and WRITE operation
* Fast cl
Applications
* that benefit from a high-speed, fully-utilized DDR data bus. Please refer to Micron’s Web site (www. micron. com/ sramds) for the latest data sheet. READ/WRITE OPERATIONS
All bus transactions operate on an uninterruptable burst of two data, requiring one full clock cycle of bus utilization. The resul