EDW2032BBBG - GDDR5 SGRAM

Product Overview

Micron

Datasheet Details

Part number	EDW2032BBBG
Manufacturer	Micron
File Size	237.27 KB
Description	GDDR5 SGRAM
Datasheet	EDW2032BBBG Datasheet
Additional preview pages of the EDW2032BBBG datasheet.

Product details

Description

2Gb: x16, x32 GDDR5 SGRAM Ball Assignments and Descriptions Figure 2: 170-Ball FBGA MF = 0 (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A VSSQ DQ1 VSSQ DQ0 NC B VDDQ DQ3 VDDQ DQ2 VSS C VSSQ EDC0 VSSQ VSSQ VDD D VDDQ DBI0_n VDDQ WCK01_t WCK01_c E VSSQ DQ5 VSSQ DQ4 VDDQ F VDDQ DQ7 VDDQ DQ6 VSSQ G VDD VDDQ RAS_n VDD VSS H VSS VSSQ VDDQ A10, A0 A9, A1 J MF RESET_n CKE_n ABI_n A12, RFU K VSS VSSQ VDDQ A8, A7 A11, A6 L VDD VDDQ CAS_n VDD

Features

GDDR5 SGRAM EDW2032BBBG.
4 Meg x 32 I/O x 16 banks, 8 Meg x 16 I/O x 16 banks Features.
VDD = VDDQ = 1.6V/1.5V ±3% and 1.35V ±3%.
Data rate: 5.0 Gb/s, 6.0 Gb/s, 7.0 Gb/s (MAX).
16 internal banks.
Four bank groups for tCCDL = 3 tCK.
8n-bit prefetch architecture: 256-bit per array read or write access for x32; 128-bit for x16.
Burst length (BL): 8 only.
Programmable CAS latency: 6.
22.
Programmable WRITE laten.

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Published: Aug 13, 2015 |