* ITEM tCLK tRAS tRCD tAC tRC Icc1 Icc6 Clock Cycle Time (Min.) (Min.) (Min.) (Max.) (CL=3) (Min.) M2V64S20TP M2V64S30TP M2V64S40TP -6 7.5ns 45ns 20.0ns 5.4ns 67.5ns 120mA (Max.) 1mA Active to Precharge Command Period Row to Column Delay Access Time from CLK Ref/Active Command Period Operation Curren
S40B
Mitsubishi Electric Semiconductor
655.47 KB
64m bit synchronous dram.
PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M.
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