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M2V64S20BTP-6

64M bit Synchronous DRAM

M2V64S20BTP-6 Features

* ITEM tCLK tRAS tRCD tAC tRC Icc1 Icc6 Clock Cycle Time (Min.) (Min.) (Min.) (Max.) (CL=3) (Min.) M2V64S20TP M2V64S30TP M2V64S40TP -6 7.5ns 45ns 20.0ns 5.4ns 67.5ns 120mA (Max.) 1mA Active to Precharge Command Period Row to Column Delay Access Time from CLK Ref/Active Command Period Operation Curren

M2V64S20BTP-6 General Description

M2V64S20BTP is organized as 4-bank x4,194,304-word x 4-bit,and M2V64S30BTP is organized as 4-bank x 2097152-word x 8-bit ,and M2V64S40BTP is organized as 4-bank x 1048576-word x 16-bit Synchronous DRAM with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. M2V64S20BTP.

M2V64S20BTP-6 Datasheet (655.47 KB)

Preview of M2V64S20BTP-6 PDF

Datasheet Details

Part number:

M2V64S20BTP-6

Manufacturer:

Mitsubishi

File Size:

655.47 KB

Description:

64m bit synchronous dram.
PC133 SDRAM (Rev.0.5) Oct. '99 64M bit Synchronous DRAM M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M.

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M2V64S20BTP-6 64M bit Synchronous DRAM Mitsubishi

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