M2V64S30BTP Datasheet - Mitsubishi

64M bit Synchronous DRAM

M2V64S30BTP Features

* - Single 3.3v ± 0.3v power supply - Clock frequency 125MHz /100MHz - Fully synchronous operation referenced to clock rising edge - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/Full Page (programmable) - Burst type- sequential / int

M2V64S30BTP General Description

The M2V64S20BTP is organized as 4-bank x 4194304-word x 4-bit, M2V64S30BTP is organized as 4-bank x 2097152-word x 8-bit, and M2V64S40BTP is organized as 4-bank x 1048576-word x 16-bit Synchronous DRAM with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M2V64S2.

M2V64S30BTP Datasheet (674.37 KB)

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M2V64S30BTP

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Mitsubishi

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674.37 KB

Description:

64m bit synchronous dram.
SDRAM (Rev.1.2) Apr. '99 64M bit Synchronous DRAM MITSUBISHI LSIs M2V64S20BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP.

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M2V64S30BTP 64M bit Synchronous DRAM Mitsubishi

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M2V64S30BTP Features

M2V64S30BTP General Description

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