26LS32 - 3-LINE RECEIVER

Motorola Inc

Datasheet Details

four independent receiver chains which comply with EIA Standards for the Electrical Characteristics of Balanced/Unbalanced Voltage Digital Interface Circuits. Receiver outputs are 74LS compatible, three.
state structures which are forced to a high impedance state when Pin 4 is a Logic “0” and Pin 12 is a Logic “1.” A PNP device buffers each output control pin to assure minimum loading for either Logic “1” or Logic “0” inputs. In addition, each receiver chain has internal hysteresis circui.

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Published: Mar 23, 2005 |