MPC8360E Datasheet (Motorola Semiconductor)

MPC8360E, Processor

Part II *Reset and Configuration Reset, Clocking, and Initialization System Configuration Part III *Core and I/O Interfaces Arbiter and Bus Monitor e300 Processor Core Overview Integrated Programmable Interrupt Controller (IPIC) DDR Memory Controller Local Bus Controller Sequencer DMA

www.DataSheet4U.com MPC8360E PowerQUICC™ II Pro Integrated Communications Processor Family Reference Manual MPC8360ERM Rev.

1 09/2006 Preliminary Subject to Change Without Notice www.DataSheet4U.com How to Reach Us: Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N.

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MPC8360E Features

* of the QUICC Engine Block Compared with the CPM 1-13 Software Migration from the MPC82xx/MPC85xx Family Devices 1-14 Serial Protocol Table 1-15 QUICC Engine Configurations 1-16 Security Engine 1-16 Dual DDR Memory Controllers 1-17 PCI Controller 1-18 PCI Bus Arbitration Unit 1-18 Local Bus Contr