MC14569B Datasheet - Motorola

MC14569B Programmable Divide-By-N Dual 4-Bit Binary/BCD Down Counter

INPUTS P0, P1, P2, P3 (Pins 3, 4, 5, 6) * Preset Inputs. Programmable inputs for the least significant counter. May be binary or BCD depending on the control input. P4, P5, P6, P7 (Pins 11, 12, 13, 14) * Preset Inputs. Programmable inputs for the most significant counter. May be bin.

MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14569B Programmable Divide-By-N Dual 4-Bit Binary/BCD Down Counter The MC14569B is a programmable divide by N dual 4 bit binary or BCD down counter constructed with MOS P channel and N channel enhancement mode devices (complementary MOS) in a monolithic structure. This device has been designed for use with the MC14568B phase comparator/counter in frequency synthesizers, phase locked loops, and other frequen.

MC14569B Features

* CTL2 CLOCK MC14569B 4 MOTOROLA CMOS LOGIC DATA Table 1. Mode Controls (Cascade Feedback = Low) Counter Control Values CTL1 0 0 1 1 CTL2 0 1 0 1 Divide Ratio Zero Detect 256 160 160 100 Q 256 160 160 100 NOTE: Data Preset Inputs (P0

* P7) are “Don’t Cares” while Cascade Feedback is Low. T

MC14569B Datasheet (323.55 KB)