MCM62110 Datasheet (Motorola) - 32K x 9 Bit Synchronous Dual I/O or Separate I/O Fast Static RAM with Parity Checker

MCM62110, 32K x 9 Bit Synchronous Dual I/O or Separate I/O Fast Static RAM with Parity Checker

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM62110/D 32K x 9 Bit Synchronous Dual I/O or Separate I/O Fast Static RAM with Parity Checker The MCM62110 is a 294,912 bit synchronous static random access memory organized as 32,768 words of 9 bits, fabricated using Motorola’s high performance silicon gate CMOS technology.

The device integrates a 32K x 9 SRAM core with advanced peripheral circuitry consisting of address registers, two sets of input data registers

MCM62110 Features

* nced to VSS = VSSQ = 0 V) Parameter Supply Voltage (Operating Voltage Range) Output Buffer Supply Voltage (5.0 V TTL Compatible) (3.3 V 50 Ω Compatible) Input High Voltage Input Low Voltage

* VIL (min) =

* 3.0 V ac (pulse width ≤ 20 ns) Symbol VCC VCCQ VIH VIL Min 4.5 4.5 3.