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MPC755 - RISC Microprocessor Hardware Specifications

Datasheet Summary

Description

31 System Design Information

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Features

  • processing unit.
  • Four instructions fetched per clock.
  • One branch processed per cycle (plus resolving two speculations).
  • Up to one speculative stream in execution, one additional speculative stream in fetch.
  • 512-entry branch history table (BHT) for dynamic prediction.
  • 64-entry, four-way set-associative branch target instruction cache (BTIC) for eliminating branch delay slots.
  • Dispatch unit.
  • Full hardware detection of dependencies (re.

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Datasheet Details

Part number MPC755
Manufacturer Motorola
File Size 1.61 MB
Description RISC Microprocessor Hardware Specifications
Datasheet download datasheet MPC755 Datasheet
Additional preview pages of the MPC755 datasheet.

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Full PDF Text Transcription

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Freescale Semiconductor Technical Data MPC755EC Rev. 6.1, 01/2005 MPC755 RISC Microprocessor Hardware Specifications This document is primarily concerned with the MPC755; however, unless otherwise noted, all information here also applies to the MPC745. The MPC755 and MPC745 are PowerPC™ microprocessors. The MPC755 and MPC745 are reduced instruction set computing (RISC) microprocessors that implement the PowerPC instruction set architecture. This document describes pertinent physical characteristics of the MPC755. For functional characteristics of the processor, refer to the MPC750 RISC Microprocessor Family User’s Manual. To locate any published errata or updates for this document, refer to the website at http://www.freescale.com. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Contents Overview . . . .
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