XPC855TZP80D4 - (XPC860 Series) Family Hardware Specifications

Motorola

Datasheet Details

re) with thirty-two 32-bit general-purpose registers (GPRs).
The core performs branch prediction with conditional prefetch without conditional execution.
4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1).
16-Kbyte instruction caches are four-way, set-associative with 256 sets; 4-Kbyte instruction caches are two-way, set-associative with 128 sets.
8-Kbyte data caches are two-way, set-associative with 256 sets; 4-Kbyte data caches are.

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Published: Apr 12, 2006 |