High-performance 32-bit architecture for embedded control application.
32-bit separate address/data bus.
1-Kbyte cache memory.
Pipeline structure of 1 clock pitch 16-bit fixed instructions (with some exceptions) 32-bit general-purpose registers: 32 4-Gbyte linear address space.
Register/flag hazard interlocked by hardware Dynamic bus sizing function (16 bits) 16-bit bus fixing function 16-bit bus system can be configured. Instruc.
