S7S3218U2M Datasheet - NETSOL

S7S3218U2M 1Mx36 & 2Mx18 Quadruple-II+ BL2 SRAM

The S7S3236U2M and S7S3218U2M are 37,748,736-bits Quadruple Synchronous Pipelined Burst SRAMs. They are organized as 1,048,576 words by 36bits for S7S3236U2M, 2,097,152 words by 18bits for S7S3218U2M. The Quadruple operation is possible by supporting DDR read and write operations through separate da.

SSSS7777SSSS3333222231316868UUUU2222MMMM 11MMxx3366&&22MMxx1188QQuuaaddrruuppllee IIII++BBLL22SSRRAAMM 36Mb Quadruple-II+ BL2 SRAM Specification (2.5 Clock Read Latency) 165FBGA with Pb & Pb Free (ROHS Compliant) NETSOL RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This do.

S7S3218U2M Features

* Key Parameters

* 1.8V+0.1V/-0.1V Power Supply.

* DLL circuitry for wide output data valid window and future fre- quency scaling.

* I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/ -0.1V for 1.8V I/O.

* Separate independent read and write data ports with c

S7S3218U2M Datasheet (416.86 KB)