4011B Datasheet | NXP Semiconductors

DESCRIPTION The HEF4011B provides the positive quadruple 2-input NAND function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance. HEF4011B gates Fig.2 Pinning diagram. HEF4011BP(N): HEF4011BD(F): Fig.1 Functional diagram. HEF4011BT(D): 14-lead DIL; plastic (SOT27-1) 14-lead DIL; ceramic (cerdip) (SOT73) 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America Fig.3 Logic diagram (one gate). FAMILY DATA, IDD LIMITS category GATES See Family Specifications January 1995 Philips Semiconductors Product specification Quadruple 2-input NAND gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 p F; input transition times ≤ 20 ns VDD V Propagation delays In → On Output transition times HIGH to LOW 5 10 15 5 10 15 5 LOW to HIGH 10 15 t TLH t THL t PHL; t PLH SYMBOL TYP 55 25 20 60 30 20 60 30 20 MAX 110 45 35 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns HEF4011B gates TYPICAL EXTRAPOLATION FORMULA 28 ns + (0,55 ns/p F) CL 14 ns + (0,23 ns/p F) CL 12 ns + (0,16 ns/p F) CL 10 ns + (1,0 ns/p F) CL 9 ns + (0,42 ns/p F) CL 6 ns + (0,28 ns/p F) CL 10 ns + (1,0 ns/p F) CL 9 ns + (0,42 ns/p F) CL 6 ns + (0,28 ns/p F) CL VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (µW) 1300 fi + ∑ (fo CL) × VDD2 6000 fi + ∑ (fo CL) × 20 100 fi + ∑ (fo CL) × VDD2 VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (p F) ∑ (fo CL) = sum of outputs VDD = supply voltage (V) January...