* individual J, K, clock (CPn), set (SD), and reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the function table regardless of the level at the other inputs. A High level on the clock (CPn) input enables the J and K inpu
74ALS112A Datasheet (92.64 KB)
74ALS112A
92.64 KB
Dual j-k negative edge-triggered flip-flop.
INTEGRATED CIRCUITS 74ALS112A Dual J-K negative edge-triggered flip-flop Product specification IC05 Data Handbook 1996 June 27 Philips Semiconductor.
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