74F113 Dual J-K negative edge-triggered flip-flops

NXP

Description

INTEGRATED CIRCUITS 74F113 Dual J-K negative edge-triggered flip-flops without reset Product specification IC15 Data Handbook 1991 Feb 14 Philips Se.
The 74F113, dual negative edge-triggered JK-type flip-flop, features individual J, K, clock (CP), set (SD) inputs, true and complementary outputs.

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Datasheet Specifications

Part number: 74F113
Manufacturer: NXP ↗
File Size: 81.65 KB
Datasheet: 74F113_PhilipsSemiconductors.pdf
Description: Dual J-K negative edge-triggered flip-flops

Features

* individual J, K, clock (CP), set (SD) inputs, true and complementary outputs. The asynchronous SD input, when low, forces the outputs to the steady state levels as shown in the function table regardless of the level at the other inputs. A high level on the clock (CP) input enables the J and K inputs

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74F113 Dual J-K negative edge-triggered flip-flops NXP

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